VHDL Engineer: RTL and ASIC Design

I am a digital design engineer, and my primary language is VHDL. Every day I turn specifications into clean synthesizable RTL: state machines, pipelines, arbiters, bus interfaces, clock domain crossings, and register files that actually meet timing requirements and work reliably in silicon. I pay attention to details that determine whether a block will work or destroy an expensive mask set, so I write code that the synthesizer understands, that is easy to review, and that the verification engineer trusts. Unlike a generalist leaning toward Verilog and FPGA, VHDL and ASIC methodology are not a side skill for me but the center of my work.

I deliver every block with a verification plan and self-checking testbenches in VHDL, so correctness is proven, not assumed. I build stimuli, reference models, assertions, and coverage goals, catching edge cases before they become errors on real hardware. I write and tune timing constraints, read synthesis and static timing analysis reports, close setup and hold, pass lint, CDC checks, and equivalence verification. Whether it's an FPGA prototype or a full ASIC tape-out, I keep RTL, constraints, and testbench in sync so the design reaches placement and routing without surprises.

I am equally comfortable starting with a rough specification and pulling existing codebases that need rescuing; everything I deliver I document so your team can maintain it after me. Give me the interface, clocking, and constraints — I will return readable, reusable, and routing-ready RTL.

— Synthesizable VHDL RTL: state machines, pipelines, arbiters, FIFOs, register maps
— Self-checking testbenches, reference models, assertions, and coverage
— Timing constraints, synthesis, and static timing closure
— Clock domain crossings, reset strategy, lint, and CDC
— ASIC and FPGA routing from simulation to placement and routing