Vyacheslav
He graduated from BSUIR in 2012. I work as a software engineer. I worked with: FPGA Xilinx (virtex 6, spartan 6, Zynq). Developed modules on VHDL (DOS, finite machines, interfaces) Interfaces uart, sp…
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He graduated from BSUIR in 2012. I work as a software engineer. I worked with: FPGA Xilinx (virtex 6, spartan 6, Zynq). Developed modules on VHDL (DOS, finite machines, interfaces) Interfaces uart, sp…
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