Translation of code from VHDL to Verilog
Employer
Eduard
Project parameters
Type of cooperationOne-time project
SectionSoftware development
Prepaymentprepayment is possible
Payment methodsBank transfer, Electronic money
Acceptance of requestsfrom Jul 4, 2022 until Jul 11, 2022
Project description
Programmer services are required. There is a program on VHDL - DES encryptor, which implements a substitution block in S-blocks. All you have to do is transfer the code from VHDL to Verilog.
