Solve the problem in the VHDL language

Employer
[no-member:pro]Mark[/no-member:pro]
Project parameters
Type of cooperationOne-time project
SectionEducation and consulting
Prepaymentprepayment is possible
Payment methodsCash, Bank transfer, Electronic money
Acceptance of requestsfrom Jun 27, 2022 until Jul 2, 2022
Project description
Offering extra earnings. You need to solve a simple problem in the VHDL language (synthesized model and testbench). It should be resolved within 30-40 minutes (maximum hour).