Design of the SCRS block for the FPLS
Employer
Aleksandr
Project parameters
Type of cooperationOne-time project
SectionEngineering. Drawings
Prepaymentwithout prepayment
Payment methodsBank transfer
Acceptance of requestsfrom Apr 29, 2021 until May 9, 2021
Project description
Offering extra earnings. It is required to design a block of SKZ on the FPGA, which will receive an 8-bit code, transformations occur inside the block and the output code is also 8-bit. Code is desirable as simple as possible
