Opis projektu
Offering extra earnings. You need to connect the OLED display to the Xilinx PLIS over SPI.
1. OLED display 2.8 inches, 256x64 dots, driver ssd1322;
2. FPGA Xilinx 3s250e-144;
Task: connection of the display to the PLYSIN by 3 wire SPI, display of text information (mode names) and data from the incremental encoder (0-100).
Language: Verilog, SV:
From you: code on verilog/SV and testbench for ISim or ModelSim.
Payment: YAKA.
1. OLED display 2.8 inches, 256x64 dots, driver ssd1322;
2. FPGA Xilinx 3s250e-144;
Task: connection of the display to the PLYSIN by 3 wire SPI, display of text information (mode names) and data from the incremental encoder (0-100).
Language: Verilog, SV:
From you: code on verilog/SV and testbench for ISim or ModelSim.
Payment: YAKA.
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